S T U/D4530NLS
S amHop Microelectronics C orp.
Dec 28 , 2005
N-C hannel Logic Level E nhancement Mode Field E ffect
Transistor
P R ODUC T S UMMAR Y
V DS S
www.
DataSheet4U.
com
F E AT UR E S
( mW)
ID
53A
R DS (ON)
8
T yp
S uper high dense cell design for low R DS (ON ).
@ V G S = 10V @ V G S = 4.
5V
R ugged and reliable.
TO-252 and TO-251 P ackage.
D
35V
10
D G S
G D
S
G
S TU S E R IE S TO-252AA(D-P AK)
S TD S E R IE S TO-251(l-P AK)
S
ABS OLUTE MAXIMUM R ATINGS (Ta=25 C unless otherwise noted)
P arameter Drain-S ource Voltage R ating Drain-S ource Voltage Gate-S ource Voltage Drain C urrent-C ontinuous a -P ulsed @ T C =25 C S ymbol Vspike (c) V DS V GS ID IDM IS PD T J , T S ...