August 2004 rev 2.
0 DDR 14-Bit Registered Buffer ASM4SSTVF16857 LVCMOS level at a valid logic state since VREF may Features • Fully JEDEC JC40 - JC42.
5 compliant for DDR1 applications to include: PC1600, PC2100, PC2700 & PC3200 ( JEDEC defined DDR 400 @ 200MHz ) www.
DataSheet4U.
com • Low voltage operation; VDD: 2.
3V - 2.
7V.
not be stable during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic low level during power-up.
In the JEDEC defined Registered DDR DIMM • • • SSTL_2 Class II outputs.
Differential clock inputs.
Available in 48 pin TSSOP and TVSOP packages.
application, RESETB is specified to be...

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