CY2SSTV16857 14-Bit Registered Buffer PC2700-/PC3200-Compliant Features • Differential Clock Inputs up to 280 MHz • Supports LVTTL switching levels on the RESET pin • Output drivers have controlled edge rates, so no www.
DataSheet4U.
com external resistors are required • Two KV ESD protection • Latch-up performance exceeds 100 mA: JESD78, Class II • Conforms to JEDEC STD (JESD82-3) for buffered DDR DIMMs • 48-pin TSSOP When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and REF voltage inputs are allowed.
In addition, when RESET is LOW, all registers are reset and all outputs force to the LOW state.
The LVCMOS RESET input must always be held a...

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)