November 2004 ® AS7C33512NTF18A 3.
3V 512K×18 Flowthrough Synchronous SRAM with NTDTM Features • Organization: 524,288 words × 18 bits • NTD™ architecture for efficient bus operation • Fast clock to data access: 7.
5/8.
5/10 ns • Fast OE access time: 3.
5/4.
0 ns • Fully synchronous operation • Flow-through mode • Asynchronous output enable control www.
DataSheet4U.
com • Available in 100-pin TQFP • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 3.
3 core power supply • 2.
5V or 3.
3V I/O operation with separate VDDQ • 30 mW typical standby power • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Logic...

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