1CY 7C33 5 fax id: 6018 CY7C335 com Universal Synchronous EPLD Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock select multiplexer — Feed back multiplexer • • • • • • • • • • — Output enable (OE) multiplexer Bypass on input and output registers All twelve macrocell state registers can be hidden User configurable I/O macrocells to implement JK or RS flip-flops and T or D registers Input multiplexer per pair of I/O macrocells allows I/O pin associated with a hidden macrocell state register to be saved for use as an input Four dedicated hidden registers Twelve dedicated re...

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