| Part Number | CY7C1212H |
| Manufacturer | Cypress Semiconductor |
| Title | 1-Mbit (64K x 18) Pipelined Sync SRAM |
| Description | 1] The CY7C1212H SRAM integrates 64K x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst opera... |
| Features |
• Registered inputs and outputs for pipelined operation • 64K × 18 common I/O architecture • 3.3V core power supply (VDD) • 2.5V/3.3V I/O power supply (VDDQ) • Fast clock-to-output times — 3.5 ns (for 166-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supp... |
| File Size | 395.05KB |
| Datasheet |
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CY7C1212F : 1] The CY7C1212F SRAM integrates 65,536 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe.