COTS PEM Austin Semiconductor, Inc.
AS5SP128K32DQ SSRAM 4.
0Mb, 128K x 32, Synchronous SRAM Pipeline Burst, Single Cycle Deselect Features • • • • • • • • • • • • • • • • • Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Control Registers Byte Write support Global Write support On-Chip low power mode [powerdown] via ZZ pin Interleaved or Linear Burst support via Mode pin Three Chip Enables for ease of depth expansion without Data Contention.
Two Cycle load, Single Cycle Deselect Asynchronous Output Enable (OE\) Three Pin Burst Control (ADSP...

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