98 97 96 95 92 91 89 87 84 99 94 93 90 88 86 85 83 DQPc DQc DQc VDDQ VSSQ 100 82 81 9.
0Mb, 256K x 36, Synchronous SRAM Pipeline Burst, Single Cycle Deselect 1 2 3 4 5 6 7 8 9 A A CE1\ CE2 BWd\ BWc\ BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A Austin Semiconductor, Inc.
Plastic Encapsulated Microcircuit CO TS PEM COTS SSRAM AS5SP256K36DQ 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 FEATURES • Synchronous Operation in relation to the input Clock DQc DQc • 2 Stage Registers resulting in Pipeline operation DQc DQc • On chip address counter (base +3) for Burst operations VSSQ VDDQ • Self-Timed Write Cycles DQc ...

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