COTS PEM Austin Semiconductor, Inc.
AS5SP512K18DQ SSRAM 9Mb, 512K x 18, Synchronous SRAM Pipeline Burst, Single Cycle Deselect NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 98 97 96 95 92 91 89 87 84 99 94 93 90 88 86 85 83 100 82 81 A A CE1\ CE2 NC NC BWb\ BWa\ CE3\ VDD VSS CLK GW\ BWE\ OE\ ADSC\ ADSP\ ADV\ A A Plastic Encapsulated Microcircuit 80 79 78 77 76 75 74 73 72 71 70 69 68 67 Features • • • • • • • • • • • • • • • • • Synchronous Operation in relation to the input Clock 2 Stage Registers resulting in Pipeline operation On chip address counter (base +3) for Burst operations Self-Timed Write Cycles On-Chip Address and Co...

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