DATA SHEET 512M bits DDR SDRAM WTR (Wide Temperature Range) EDD5108ADTA-LI (64M words × 8 bits) EDD5116ADTA-LI (32M words × 16 bits) Description The EDD5108AD and the EDD5116AD are 512M bits Double Data Rate (DDR) SDRAM.
Read and write operations are performed at the cross points of the CK and the /CK.
This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture.
Data strobe (DQS) both for read and write are available for high speed and reliable data bus design.
By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable.
Pin Configurations /xxx indicates active low signal.
66-pin Plastic TSOP(II) VDD VDD DQ0 DQ0 VDDQ VDDQ ...

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