NB7V586M 1.
8V Differential 2:1 Mux Input to 1.
2V/1.
8V 1:6 CML Clock/Data Fanout Buffer / Translator Description Multi−Level Inputs w/ Internal Termination The NB7V586M is a differential 1−to−6 CML Clock/Data Distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin.
The INx/INx inputs incorporate internal 50 W termination resistors and will accept differential LVPECL, CML, or LVDS logic levels (see Figure 12).
The INx/INx inputs and core logic are powered with a 1.
8 V supply.
The NB7V586M produces six identical differential CML output copies of Clock or Data.
The outputs are configured as three banks of two differential pair.
Each bank (or all three banks) have...

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