Part Number
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QL3004E |
Manufacturer
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QuickLogic Corporation |
Description
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PLD Gate pASIC 3 FPGA Combining High Performance and High Density |
Published
|
May 22, 2010 |
Detailed Description
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Datasheet
|
QL3004E
|
Overview
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Two array clock/control networks available
4,000 Usable PLD Gates with 82 I/Os
Counters, 400 MHz Datapaths 0.
35 µm four-layer metal non-volatile CMOS process for smallest die sizes
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100% routable with 100% utilization and
to the logic cell flip-flop clock, set and reset inputs — each driven by an input-only pin Two global clock/control networks available to the logic cell; F1, clock, set and reset inputs ...
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