and benefits „ „ „ „ SNR, 72.5 dBFS; SFDR, 88 dBc Sample rate up to 125 Msps 16-bit pipelined ADC core Clock input divider by 2 for less jitter contribution „ Single 3 V supply „ Flexible input voltage range: 1 V to 2 V (peak-to-peak). „ CMOS or LVDS...

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