Part Number
|
CY7C1243KV18 |
Manufacturer
|
Cypress Semiconductor |
Description
|
36-Mbit QDR II SRAM 4-Word Burst Architecture |
Published
|
Apr 15, 2011 |
Detailed Description
|
36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency)
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture ...
|
Datasheet
|
CY7C1243KV18
|
Overview
36-Mbit QDR II+ SRAM 4-Word Burst Architecture (2.
0 Cycle Read Latency)
36-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.
0 Cycle Read Latency)
CY7C1241KV18, CY7C1256KV18 CY7C1243KV18, CY7C1245KV18 ®
Features
■
Configurations
With Read Cycle Latency of 2.
0 cycles: CY7C1241KV18 – 4 M × 8 CY7C1256KV18 – 4 M × 9 CY7C1243KV18 – 2 M × 18 CY7C1245KV18 – 1 M × 36
Separate independent read and write data ports ❐ Supports concurrent transactions 450 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double data rate (DDR) interfaces on both read and write ports (data transferred at 900 MHz) at 450 MHz Available in 2.
0 clock cycle latency Two input clocks (K and K) for p...
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