PROCESS
Power
Transistor
CP630
PNP - Silicon Darlington
Transistor Chip
com
PROCESS DETAILS Process Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization GEOMETRY GROSS DIE PER 4 INCH WAFER EPITAXIAL PLANAR 80 x 80 MILS 8.
0 MILS 18 x 27 MILS 34 x 34 MILS Al - 30,000Å Ti/Pd/Ag - 20,000Å
1,445
PRINCIPAL DEVICE TYPES CZT127 CJD127
R2 (22-March 2010)
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PROCESS
CP630
Typical Electrical Characteristics
R2 (22-March 2010)
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