PROCESS
Small Signal
Transistor
CP782X
PNP - Low VCE(SAT)
Transistor Chip
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PROCESS DETAILS Die Size Die Thickness Base Bonding Pad Area Emitter Bonding Pad Area Top Side Metalization Back Side Metalization 26 x 26 MILS 5.
9 MILS 5.
5 x 5.
5 MILS 5.
5 x 5.
5 MILS Al - 30,000Å Au - 12,000Å
GEOMETRY GROSS DIE PER 5 INCH WAFER 25,536 PRINCIPAL DEVICE TYPES CMLT7820G CMPT7820 CXT7820
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PROCESS
CP782X
Typical Electrical Characteristics
R0 (9-September 2010)
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