HD74HC166 Parallel-load 8-bit Shift Register Description This device is an 8-bit shift register with an output from the last stage.
Data may be loaded into the register either in parallel or in serial form.
When the Shift/Load input is low, the data is loaded asynchronously in parallel.
When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock.
Clear is asynchronous and active-low.
The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.
Features • • • • • High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF) High Output Current...

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