AX1250ES
2A Sink/Source Bus Termination
Regulator
GENERAL DESCRIPTION The AX1250ES is a simple, cost-effective and high-speed linear
regulator designed to generate termination voltage in double data rate (DDR) memory system to comply with the JEDEC SSTL_2 and SSTL_18 or other specific interfaces such as HSTL, SCSI-2 and SCSI-3 etc.
devices requirements.
The
regulator is capable of actively sinking or sourcing up to 2A while regulating an output voltage to within 40mV.
The output termination voltage cab be tightly regulated to track 1/2VDDQ by two external voltage divider resistors or the desired output voltage can be programmed by externally forcing the REFEN pin voltage.
The AX1250ES als...