Part Number
|
NE33200 |
Manufacturer
|
California Eastern |
Description
|
SUPER LOW NOISE HJ FET |
Published
|
Aug 9, 2014 |
Detailed Description
|
SUPER LOW NOISE HJ FET
NE33200
FEATURES
• VERY LOW NOISE FIGURE: 0.75 dB typical at 12 GHz
Optimum Noise Figure, NFOPT...
|
Datasheet
|
NE33200
|
Overview
SUPER LOW NOISE HJ FET
NE33200
FEATURES
• VERY LOW NOISE FIGURE: 0.
75 dB typical at 12 GHz
Optimum Noise Figure, NFOPT (dB)
4 3.
5
NOISE FIGURE & ASSOCIATED GAIN vs.
FREQUENCY VDS = 2 V, IDS = 10 mA
24 21 18 15 12 9 6 NF 0.
5 0 1 10 30 3 0
• HIGH ASSOCIATED GAIN: 10.
5 dB Typical at 12 GHz • GATE LENGTH: 0.
3 µm • GATE WIDTH: 280 µm
3 2.
5 2 1.
5 1
DESCRIPTION
The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to create a two-dimensional electron gas layer with very high electron mobility.
Its excellent low noise figure and high associated gain make it suitable for commercial and industrial applications.
NEC's stringent quality ass...
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