GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock January 2000 Revised February 2000 GTLP17T616 17-Bit LVTTL/GTLP Bus Transceiver with Buffered Clock General Description The GTLP17T616 is a 17-bit registered bus transceiver that provides LVTTL to GTLP signal level translation.
It allows for transparent, latched and clocked modes of data flow and provides a buffered GTLP (CLKOUT) clock output from the LVTTL CLKAB.
The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP logic levels.
High speed backplane operation is a direct result of GTLP’s reduced output swing (1V), reduced input threshold levels and output...

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