| Part Number | R5F5631JHDFC |
| Manufacturer | Renesas |
| Title | 100-MHz 32-bit RX MCU |
| Description | Maximum operating frequency: 100 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock)... |
| Features |
RX63N Group, RX631 Group
Renesas MCUs
R01DS0098EJ0180
100-MHz 32-bit RX MCU, on-chip FPU, 165 DMIPS, up to 2-MB flash memory, various communications interfaces including Ethernet MAC,
Rev.1.80 May 13, 2014
full-speed USB 2.0 host/function/OTG interface, CAN, 10- & 12-bit A/D
converters, RTC
...
|
| File Size | 1.50MB |
| Datasheet |
|
R5F5631JHDFB : Maximum operating frequency: 100 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits Memory protection unit (MPU) Single precision (32-bit) floating point Data .
R5F5631JHDFP : Maximum operating frequency: 100 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Nine 32-bit registers Accumulator: One 64-bit register Basic instructions: 73 Floating-point instructions: 8 DSP instructions: 9 Addressing modes: 10 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 x 32 64 bits On-chip divider: 32 / 32 32 bits Barrel shifter: 32 bits Memory protection unit (MPU) Single precision (32-bit) floating point Data .