T R I Q U I N T S E M I C O N D U C T O R, I N C .
Figure 1.
Block Diagram FBIN 11 GA1085 S1 10 REFCLK 9 S0 8 F1 7 F0 6 GND 5 TEST 12 VDD 13 Phase Detector VCO Phase Select 4 VDD 3 2 Q10 Q9 11-Output Configurable Clock Buffer Q0 14 GND 15 Q1 Q2 16 17 MUX Divide Logic ÷4, ÷5, or ÷6 Output Buffers Group A Group C 1 GND 28 27 Q8 Q7 Features • Wide frequency range: 24 MHz to 105 MHz • Output configurations: Four outputs at fREF Four outputs at fREF /2 Two outputs at fREF /2 ␣ ␣ ␣ ␣ with adjustable phase ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ ␣ or Five outputs at 2x fREF Three outputs at fREF Two outputs at fREF ␣ ␣ ␣ ␣ with adjustable phase • Selectable Phase Shift: –2t, –t, +t, and +2t ...

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