DDR SDRAM (Rev.
1.
2) Jun.
'01 Preliminary MITSUBISHI LSIs M2S56D20/ 30/ 40ATP 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents are subject to change without notice.
DESCRIPTION M2S56D20ATP is a 4-bank x 16,777,216-word x 4-bit, M2S56D30ATP is a 4-bank x 8,388,608-word x 8-bit, M2S56D40ATP is a 4-bank x 4,194,304-word x 16-bit, double data rate synchronous DRAM, with SSTL_2 interface.
All control and address signals are referenced to the rising edge of CLK.
Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK.
The M2S56D20/30/40ATP achieves very high speed data rate up to 133MHz, and are suitable for ma...

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