Revision History Revision 0.
1 (May.
2010) - First release.
Revision 0.
2 (Sep.
2010) - Delete CL=2 parameters - Input Leakage Current = -2μA ~ +2μA - Change Supply Voltage Rating = -0.
5 ~ +2.
3 - Delete Deep Power Down Mode - Change AC timing paramters: tRC & tIS Revision 0.
3 (Nov.
2010) - Change clock input capacitance value EM48AM3284LBB Nov.
2010 www.
eorex.
com 1/22 EM48AM3284LBB 512Mb (4M×4Bank×32) Mobile Synchronous DRAM Features • Fully Synchronous to Positive Clock Edge • VDD= 1.
7V~1.
95V for 133MHz & 166MHz Power Supply • LVCMOS Compatible with Multiplexed Address • Programmable Burst Length (B/L) - 1, 2, 4, 8 or Full Page • Programmable CAS Latency (C/L) - 3 • Data Mask (DQM) for ...

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