Part Number
|
SI53106 |
Manufacturer
|
Silicon Laboratories |
Description
|
SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER |
Published
|
Mar 4, 2016 |
Detailed Description
|
Si53106
SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER
Features
Six 0.7 V low-power, push-pull, Low phase jitter ...
|
Datasheet
|
SI53106
|
Overview
Si53106
SIX-OUTPUT PCIE GEN 3 BUFFER/ZERO DELAY BUFFER
Features
Six 0.
7 V low-power, push-pull, Low phase jitter (Intel QPI, PCIe
HCSL-compatible PCIe Gen 3 Gen 1/2/3/4 common clock
outputs
compliant
Individual OE HW pins for each Gen 3 SRNS Compliant
output clock
PLL or bypass mode
100 MHz /133 MHz PLL
Spread spectrum tolerable
operation, supports PCIe and QPI
PLL bandwidth SW SMBUS programming overrides the latch
value from HW pin
1.
05 to 3.
3 V I/O supply voltage
50 ps output-to-output skew
Industrial Temperature: –40 to 85 °C
SMBus address configurable to allow multiple buffers in a single
40-pin QFN For higher output devices or
control net...
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