Part Number
|
SI53115 |
Manufacturer
|
Silicon Laboratories |
Description
|
15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER |
Published
|
Mar 4, 2016 |
Detailed Description
|
Si53115
15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER
Features
Fifteen 0.7 V low-power, push- Separate VDDIO for ...
|
Datasheet
|
SI53115
|
Overview
Si53115
15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER
Features
Fifteen 0.
7 V low-power, push- Separate VDDIO for outputs
pull HCSL PCIe Gen3 outputs PLL or bypass mode
100 MHz /133 MHz PLL
Spread spectrum tolerable
operation, supports PCIe and QPI
PLL bandwidth SW SMBUS programming overrides the latch
1.
05 to 3.
3 V I/O supply voltage 50 ps output-to-output skew 50 ps cyc-cyc jitter (PLL mode)
value from HW pin
Low phase jitter (Intel QPI, PCIe
9 selectable SMBUS addresses
Gen 1/2/3/4 common clock compliant)
SMBus address configurable to allow multiple buffers in a single
Gen 3 SRNS Compliant
control network 3.
3 V supply 100 ps input-to-output ...
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