| Part Number | R7S910 |
| Manufacturer | Renesas |
| Title | MCUs |
| Description | Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address ... |
| Features |
■ On-chip 32-bit ARM Cortex-R4F processor High-speed realtime control with maximum operating frequency of 450/600 MHz Capable of 747/996 DMIPS (in operation at 450/600 MHz) On-chip 32-bit ARM Cortex-R4F (revision r1p4) Tightly coupled memory (TCM) with ECC: 512 Kbytes/32 Kbytes Instruction c... |
| File Size | 429.67KB |
| Datasheet |
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R7S910001CFP : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910002CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910006CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910007CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910011CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910013CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910015CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910016CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910017CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910018CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910020CBG : Maximum operating frequency 112-pin FBGA: 450 MHz 32-bit CPU Cortex-R4 designed by Arm (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC) Data cache: 8 Kbytes (with ECC) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC) BTCM: 32 Kbytes (with ECC) Instruction set: Arm v7-R architecture, so support includes Thumb® and Thumb-2 Data arrangement Instructio.
R7S910021CBG : Maximum operating frequency 112-pin FBGA: 450 MHz 32-bit CPU Cortex-R4 designed by Arm (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC) Data cache: 8 Kbytes (with ECC) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC) BTCM: 32 Kbytes (with ECC) Instruction set: Arm v7-R architecture, so support includes Thumb® and Thumb-2 Data arrangement Instructio.
R7S910022CBG : Maximum operating frequency 112-pin FBGA: 450 MHz 32-bit CPU Cortex-R4 designed by Arm (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC) Data cache: 8 Kbytes (with ECC) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC) BTCM: 32 Kbytes (with ECC) Instruction set: Arm v7-R architecture, so support includes Thumb® and Thumb-2 Data arrangement Instructio.
R7S910023CBG : Maximum operating frequency 112-pin FBGA: 450 MHz 32-bit CPU Cortex-R4 designed by Arm (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC) Data cache: 8 Kbytes (with ECC) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC) BTCM: 32 Kbytes (with ECC) Instruction set: Arm v7-R architecture, so support includes Thumb® and Thumb-2 Data arrangement Instructio.
R7S910101CFP : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.
R7S910102CBG : Maximum operating frequency 320-pin FBGA: 600 MHz 176-pin HLQFP: 450 MHz 32-bit CPU Cortex-R4F designed by ARM (core revision r1p4) Address space: 4 Gbytes Instruction cache: 8 Kbytes (with ECC with) Data cache: 8 Kbytes (with ECC with) Tightly coupled memory (TCM) ATCM: 512 Kbytes (with ECC with) BTCM: 32 Kbytes (with ECC with) Instruction set: ARMv7-R architecture, so support includes Thumb and Thumb-2 Data arrangement Instructions: Little endian Data: Little endian Memory protection unit (MPU) Operating frequency: 150 MHz 32-bit CPU Cortex-M3 designed by ARM (core revision r2p1) Address space: 4 Gbytes Instruction set: ARMv7-R architecture, so support includes Th.