Part Number
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54LS114 |
Manufacturer
|
National Semiconductor |
Description
|
Dual JK Flip-Flop |
Published
|
Aug 25, 2017 |
Detailed Description
|
54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
June 1989
54LS114 Dual JK Negative Edg...
|
Datasheet
|
54LS114
|
Overview
54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
June 1989
54LS114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears
General Description
The ’LS114 features individual J K and set inputs and common clock and common clear inputs When the clock goes HIGH the inputs are enabled and data will be accepted The logic level of the J and K inputs may be allowed to change
when the Clock Pulse is HIGH and the bistable will perform according to the truth table as long as the minimum setup times are observed Input data is transferred to the outputs on the negative-going edge of the clock pulse
Connection Diagram
Dual-In-Line Package
Logic Symbol
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