74AC11194 4–BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER
• Parallel-to-Serial, Serial-to-Parallel
Conversions
• Left or Right Shifts • Parallel Synchronous Loading • Direct Overriding Clear • Temporary Data Latching Capability • Flow-Through Architecture to Optimize
PCB Layout
• Center-Pin VCC and GND Configurations to
Minimize High-Speed Switching Noise
t• EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity at
125°C
• Package Options Include Plastic
Small-Outline Packages, and Standard
Plastic 300-mil DIPs
SCAS093 – NOVEMBER 1989 – REVISED APRIL 1993
DW OR N PACKAGE (TOP VIEW)
SR SER
QA QB GND
GND
GND
GND
QC QD SL SER
1 2 3 4 5 6 7 8 9 10
20 S0 19 S...