D Eight Latches in a Single Package D 3-State Bus Driving True Outputs D Full Parallel Access for Loading D Buffered Input and Output-Enable Pins D Inputs Are TTL-
Voltage Compatible D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
74ACT11373 OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS015B – JUNE 1987 – REVISED APRIL 1996
DB, DW, OR NT PACKAGE (TOP VIEW)
1Q 1 2Q 2 3Q 3 4Q ...