74ACT11544 OCTAL REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS133 – D3609, JULY 1990 – REVISED APRIL 1993
• Inputs Are TTL-
Voltage Compatible • 3-State Inverted Outputs • Back-to-Back Registers for Storage • Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
t• EPIC (Enhanced-Performance Implanted
CMOS) 1-mm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
description
This 8-bit registered transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch enable (LEAB or LEBA) and output enable (GAB or GBA) inputs are provided for each register to permit indep...