74AHC138-Q100;
74AHCT138-Q100
3-to-8 line decoder/demultiplexer; inverting
Rev.
3 — 10 September 2020
Product data sheet
1.
General description
The 74AHC138-Q100; 74AHCT138-Q100 are high-speed Si-gate
CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard No.
7A.
The 74AHC138-Q100; 74AHCT138-Q100 is a 3-to-8 line decoder/demultiplexer.
It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected.
There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3).
Every output will be HIGH unless E1 and ...