74AHC139-Q100; 74AHCT139-Q100
Dual 2-to-4 line decoder/demultiplexer
Rev.
1 — 5 June 2013
Product data sheet
1.
General description
The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed Si-gate
CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard No.
7A.
The 74AHC139-Q100; 74AHCT139-Q100 is a high-speed, dual 2-to-4 line decoder/demultiplexer.
This device has two independent decoders.
Each decoder accepts two binary weighted inputs (nA0 and nA1) and provides four mutually exclusive active LOW outputs (nY0 to nY3).
Each decoder has an active LOW enable input (nE).
When nE is HIGH, every output is forced HIGH.
The enable input c...