74AHC273-Q100;
74AHCT273-Q100
Octal D-type flip-flop with reset; positive-edge trigger
Rev.
2 — 23 September 2020
Product data sheet
1.
General description
The 74AHC273-Q100; 74AHCT273-Q100 is a high-speed Si-gate
CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).
It is specified in compliance with JEDEC standard No.
7-A.
The 74AHC273-Q100; 74AHCT273-Q100 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs.
The common clock (CP) and master reset (MR) inputs, load and reset (clear) all flip-flops simultaneously.
The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output ...