Part Number
|
74F109 |
Manufacturer
|
National Semiconductor |
Description
|
Dual JK Positive Edge-Triggered Flip-Flop |
Published
|
Nov 24, 2017 |
Detailed Description
|
54F/74F109
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
November 1994
54F/74F109 Dual JK Positive Edge-Trigger...
|
Datasheet
|
74F109
|
Overview
54F/74F109
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
November 1994
54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop
General Description
The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops.
The clocking operation is independent of rise and fall times of the clock waveform.
The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs.
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
n Guaranteed 4000V minimum ESD protection.
Ordering Code: Se...
Similar Datasheet