Part Number
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74LS114A |
Manufacturer
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Motorola |
Description
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DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP |
Published
|
Jan 24, 2014 |
Detailed Description
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SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS114A offers common clock and common clear inputs a...
|
Datasheet
|
74LS114A
|
Overview
SN54/74LS114A DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
The SN54/ 74LS114A offers common clock and common clear inputs and individual J, K, and set inputs.
These monolithic dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted.
The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up times are observed.
Input data is transferred to the outputs on the negative-going edge of the clock pulse.
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
LOW POWER SCHOTTKY
LOGIC DIAGRAM (Each Flip-Flop)
J SUFFIX CERAMIC CASE 632-08
14
Q 5...
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