74LVC138A-Q100 3-to-8 line decoder/demultiplexer; inverting Rev.
3 — 28 August 2020 Product data sheet 1.
General description The 74LVC138A-Q100 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).
The 74LVC138A features three enable inputs (E1, E2 and E3).
Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
This multiple enable function allows easy parallel expansion of the 74LVC138A-Q100 to a 1-of-32 (5 to 32 lines) decoder with just four 74LVC138A-Q100 ICs and one inverter.
The 74LVC138A-Q100 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining ...

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