com A67L9318/A67L8336 Preliminary Document Title 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM Revision History Rev.
No.
0.
0 512K X 18, 256K X 36 LVTTL, Pipelined ZeBLTM SRAM History Initial issue Issue Date July 13, 2005 Remark Preliminary PRELIMINARY (July, 2005, Version 0.
0) AMIC Technology, Corp.
com A67L9318/A67L8336 Preliminary Features Fast access time: 2.
6/2.
8/3.
2/3.
5/3.
8/4.
2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +3.
3V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and regist...

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