Dual IF Receiver AD6659
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-bit, 80 MSPS output data rate per channel
AVDD AGND
SDIO SCLK CSB
1.
8 V analog supply operation (AVDD)
SPI
CMOS OUTPUT BUFFER
1.
8 V to 3.
3 V output supply (DRVDD) Integrated noise shaping requantizer (NSR)
PROGRAMMING DATA
ORA
Integrated quadrature error correction (QEC) Performance with NSR enabled
SNR = 81 dBFS in 16 MHz band up to 30 MHz at 80 MSPS Performance with NSR disabled
SNR = 72 dBFS up to 70 MHz at 80 MSPS SFDR = 90 dBc up to 70 MHz input at 80 MSPS
E Low power: 98 mW per channel at 80 MSPS
Differential input with 700 MHz bandwidth On-chip
voltage reference and sample-and-hold circuit 2 V p-p differential an...