Data Sheet
FEATURES
8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.
3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.
3 LSB (typical),
INL = ±0.
4 LSB (typical) Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar IEEE 1596.
3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input
voltage range 1.
8 V supply operation Serial port control
Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode
APPLICATIONS
Medical imaging and nondestructive...