Data Sheet
FEATURES
Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 2.
30 GHz to 2.
65 GHz External VCO/VCXO to 2.
4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or
CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable
3 pairs of 1.
6 GHz LVPECL outputs Each output pair shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms Channel-to-channel skew paired outputs of 10 ps
Automatic synchronization of all outputs on power-up Manual output synchronization available Av...