ADC12DC105
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SNAS469B – SEPTEMBER 2008 – REVISED MARCH 2013
ADC12DC105 Dual 12-Bit, 105 MSPS A/D Converter with
CMOS Outputs
Check for Samples: ADC12DC105
FEATURES
1
•2 Internal Sample-and-Hold Circuit and Precision Reference
• Low Power Consumption • Clock Duty Cycle Stabilizer • Single +3.
0V or +3.
3V Supply Operation • Power-Down Mode • Offset Binary or 2's Complement Output Data
Format • 60-Pin WQFN Package, (9x9x0.
8mm, 0.
5mm
Pin-Pitch)
KEY SPECIFICATIONS
• Resolution: 12 Bits • Conversion Rate: 105 MSPS • SNR (fIN = 170 MHz): 69 dBFS (Typ) • SFDR (fIN = 170 MHz): 83 dBFS (Typ) • Full Power Bandwidth: 1 GHz (Typ) • Power Consumption
– 690 mW (Typ), VA = 3.
0V – 800 mW (Typ), V...