ADS5525
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ti.
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SLWS191B – JULY 2006 – REVISED MAY 2007
12-BIT, 170 MSPS ADC WITH DDR LVDS/
CMOS OUTPUTS
FEATURES
• Maximum Sample Rate: 170 MSPS • 12-Bit Resolution • No Missing Codes • Total Power Dissipation 1.
1 W • Internal Sample and Hold • 70.
5-dBFS SNR at 70-MHz IF • 84-dBc SFDR at 70-MHz IF • 11 bits ENOB Minimum at 70-MHz IF • Double Data Rate (DDR) LVDS and Parallel
CMOS Output Options
• Programmable Gain up to 6 dB for SNR/SFDR Trade-Off at High IF
• Reduced Power Modes at Lower Sample Rates
• Supports input clock amplitude down to 400 mVPP
• Clock Duty Cycle Stabilizer • No External Reference Decoupling Required • Internal and External Reference Support • Programmable Output...