December 2004 ® AS7C33128FT18B 3.
3V 128K × 18 Flow Through Synchronous SRAM Features • • • • • • • • Organization: 131,072 words × 18 bits Fast clock to data access: 6.
5/7.
5/8.
0/10.
0 ns Fast OE access time: 3.
5/4.
0 ns Fully synchronous flow through operation Asynchronous output enable control Economical 100-pin TQFP package Individual byte write and Global write Multiple chip enables for easy expansion • • • • • 3.
3V core power supply 2.
5V or 3.
3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power standby Common data inputs and data outputs www.
DataSheet4U.
com Logic block diagram LBO CLK ADV ADSC ADSP A[16:0] CLK CS CLR Burst logic 2 2 17...

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