March 2002
®
AS7C33128PFS32A AS7C33128PFS36A
3.
3V 128K X 32/36 pipeline burst synchronous SRAM
Features
• Organization: 131,072 words × 32 or 36 bits • Fast clock speeds to 200 MHz in LVTTL/LV
CMOS • Fast clock to data access: 3.
0/3.
1/3.
5/4.
0/5.
0 ns • Fast OE access time: 3.
0/3.
1/3.
5/4.
0/5.
0 ns • Fully synchronous register-to-register operation • Single register “Flow-through” mode • Single-cycle deselect • Dual-cycle deselect also available (AS7C33128PFD32A/ www.
DataSheet4U.
com AS7C33128PFD36A) • Pentium®1 compatible architecture and timing • Asynchronous output enable control • • • • • • • Economical 100-pin TQFP package Byte write enables Multiple chip enables for easy expansion 3.
3 core...