February 2005 ® AS7C332MPFD18A 3.
3V 2M × 18 pipelined burst synchronous SRAM Features • Organization: 2,097,152 words × 18 bits • Fast clock speeds to 200 MHz • Fast clock to data access: 3.
1/3.
5/3.
8 ns • Fast OE access time: 3.
1/3.
5/3.
8 ns • Fully synchronous register-to-register operation • Double-cycle deselect • Asynchronous output enable control • Available in 100-pin TQFP package www.
DataSheet4U.
com • Individual byte write and global write • • • • • • Multiple chip enables for easy expansion 3.
3V core power supply 2.
5V or 3.
3V I/O operation with separate VDDQ Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs Logic block dia...

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