Features
• Single 4.
5V - 5.
5V Supply • Serial Interface Architecture • Page Program Operation
– Single Cycle Reprogram (Erase and Program) – 512 Pages (264 Bytes/Page) Main Memory • Optional Page and Block Erase Operations • One 264-byte SRAM Data Buffer • Internal Program and Control Timer • Fast Page Program Time – 7 ms Typical • 120 µs Typical Page to Buffer Transfer Time • Low Power Dissipation – 15 mA Active Read Current Typical
– 10 µA
CMOS Standby Current Typical • 15 MHz Max Clock Frequency • Hardware Data Protection Feature • Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3 •
CMOS and TTL Compatible Inputs and Outputs • Commercial and Industrial Temperature Ranges
Descr...