CDC391 1ĆLINE TO 6ĆLINE CLOCK DRIVER WITH SELECTABLE POLARITY AND 3ĆSTATE OUTPUTS
SCAS334A − DECEMBER 1992 − REVISED NOVEMBER 1995
D Low Output Skew for Clock-Distribution
and Clock-Generation Applications
D TTL-Compatible Inputs and Outputs D Distributes One Clock Input to Six Clock
Outputs
D Polarity Control Selects True or
Complementary Outputs
D Distributed VCC and GND Pins Reduce
Switching Noise
D High-Drive Outputs (−48-mA IOH,
48-mA IOL)
D State-of-the-Art EPIC-ΙΙB Bi
CMOS Design
Significantly Reduces Power Dissipation
D Packaged in Plastic Small-Outline Package
D PACKAGE (TOP VIEW)
GND 1 1Y2 2 1Y3 3 GND 4 2Y1 5 2Y2 6 GND 7 3Y1 8
16 1Y1 15 1T/C 14 VCC 13 2T/C 12 A 11 VCC 10 3T/C 9...