CDCF2509 3.
3ĆV PHASEĆLOCK LOOP CLOCK DRIVER ą SCAS624C − APRIL 1999 − REVISED DECEMBER 2004 D Use CDCVF2509A as a Replacement for this Device D Designed to Meet PC133 SDRAM Registered DIMM Specification Rev.
0.
9 D Spread Spectrum Clock Compatible D Operating Frequency 25 MHz to 140 MHz D Static Phase Error Distribution at 66 MHz to 133 MHz is ±125 ps D Jitter (cyc−cyc) at 66 MHz to 133 MHz Is |70| ps D Available in Plastic 24-Pin TSSOP D Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications D Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs D Separate Output Enable for Each Output Bank D External Feedback (FBIN) Terminal Is Used to Synchronize the ...

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