Product Folder Order Now Technical Documents Tools & Software Support & Community CDCLVD1212 SCAS901D – SEPTEMBER 2010 – REVISED NOVEMBER 2017 CDCLVD1212 2:12 Low Additive Jitter LVDS Buffer 1 Features •1 2:12 Differential Buffer • Low Additive Jitter: 300-fs RMS in 10-kHz to 20-MHz • Low Output Skew of 35 ps (Maximum) • Universal Inputs Accept LVDS, LVPECL, and LVCMOS • Selectable Clock Inputs Through Control Pin • 12 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible • Clock Frequency: Up to 800 MHz • Device Power Supply: 2.
375 V to 2.
625 V • LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs • Industrial Temperature Range: –40°C to 85°C • Packaged in 6-mm × ...

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